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8272E–AVR–04/2013
ATmega164A/PA/324A/PA/644A/PA/1284/P
Bit 0 – TOIE1: Timer/Counter1, Overflow Interrupt Enable
When this bit is written to one, and the I-flag in the Status Register is set (interrupts globally
enabled), the Timer/Counter1 Overflow interrupt is enabled. The corresponding Interrupt Vector
(See Section “11.3” on page 55) is executed when the TOV1 Flag, located in TIFR1, is set.
16.12.13 TIMSK3 – Timer/Counter3 Interrupt Mask Register
Bit 7:6 – Reserved
These bits are unused and will always read as zero.
Bit 5 – ICIE3: Timer/Counter3, Input Capture Interrupt Enable
When this bit is written to one, and the I-flag in the Status Register is set (interrupts globally
enabled), the Timer/Counter1 Input Capture interrupt is enabled. The corresponding Interrupt
Vector (See “Interrupts” on page 61) is executed when the ICF3 Flag, located in TIFR3, is set.
Bit 4:3 – Reserved
These bits are unused and will always read as zero.
Bit 2 – OCIE3B: Timer/Counter3, Output Compare B Match Interrupt Enable
When this bit is written to one, and the I-flag in the Status Register is set (interrupts globally
enabled), the Timer/Counter3 Output Compare B Match interrupt is enabled. The corresponding
Interrupt Vector (See “Interrupts” on page 61) is executed when the OCF3B Flag, located in
TIFR3, is set.
Bit 1 – OCIE3A: Timer/Counter3, Output Compare A Match Interrupt Enable
When this bit is written to one, and the I-flag in the Status Register is set (interrupts globally
enabled), the Timer/Counter3 Output Compare A Match interrupt is enabled. The corresponding
Interrupt Vector (See “Interrupts” on page 61) is executed when the OCF3A Flag, located in
TIFR3, is set.
Bit 0 – TOIE3: Timer/Counter3, Overflow Interrupt Enable
When this bit is written to one, and the I-flag in the Status Register is set (interrupts globally
enabled), the Timer/Counter3 Overflow interrupt is enabled. The corresponding Interrupt Vector
(See “Watchdog Timer” on page 55) is executed when the TOV3 Flag, located in TIFR3, is set.
16.12.14 TIFR1 – Timer/Counter1 Interrupt Flag Register
Bit 7:6 – Reserved
These bits are unused and will always read as zero.
Bit
7
65
43
2
1
0
(0x71)
–
–ICIE3
–
OCIE3B
OCIE3A
TOIE3
TIMSK3
Read/Write
R
R/W
R
R/W
Initial Value
0
Bit
76543210
0x16 (0x36)
–
–ICF1
–
OCF1B
OCF1A
TOV1
TIFR1
Read/Write
R
R/W
R
R/W
Initial Value
00000000
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